FIG. 1 depicts a block diagram of an audio signal processing circuit 100r. The audio signal processing circuit 100r is an analog/digital mixed circuit including a digital unit 110 that handles a digital signal and an analog circuit 120 that handles an analog signal, both of which are integrated. The digital circuit 110 includes a signal processing part 112 that receives data such as digital audio data and performs predetermined signal processing on the received data. Output data of the signal processing part 112 is provided to the analog circuit 120. The analog circuit 120 converts the data DOUT from the signal processing part 112 into an analog signal AOUT and outputs the analog signal AOUT to the outside.
The digital circuit 110 further includes a frequency divider 114 that receives a clock signal (e.g., system clock signal) and divides the received clock signal to generate two clock signals CLKD and CLKA. The signal processing part 112 processes an audio signal in synchronization with the clock signal CLKD. The analog circuit 120 processes the audio data DOUT from the signal processing part 112 in synchronization with the clock signal CLKA.
In the audio signal processing circuit 100r as described above, jitters of the clock signals may cause a significant problem. FIG. 2A shows a simplified configuration of the frequency divider 114 and FIG. 2B shows a jitter of the clock signal CLKA. In the digital circuit 110, since several thousands to tens of thousands of gate elements constituting the digital circuit 110 are operated in synchronization with the clock signal CLKD, a noise N synchronized with the clock signal CLKD is superimposed on a power supply voltage VDD. Since the frequency divider 114 is operated with the power supply voltage VDD on which the noise N is superimposed, the operation speed (signal slew rate) of elements constituting the frequency divider 114 varies from moment to moment. As a result, the clock signal CLKA generated by the frequency divider 114 has a jitter corresponding to the variation in the power supply voltage VDD.
If the jitter of the clock signal CLKA is too great, the output of the analog circuit 120, mainly a D/A (digital-to-analog) converter, deviates from an expected value that would be obtained by D/A-converting the data DOUT from the signal processing part 112 at the same interval for each sampling rate. As a result, deterioration of sound quality may be caused.
FIG. 3 is a circuit diagram showing another audio signal processing circuit 100s. In this audio signal processing circuit 100s, a frequency divider 124 is formed in an analog area 122 that includes an analog circuit 120. In a system in which a power plane 116 for a digital circuit 110 and a power plane 126 for the analog circuit 120 are isolated from each other, a noise generated in the power plane 116 on the digital side is less likely to propagate to the power plane 126 on the analog side. Therefore, a jitter of the clock signal CLKA generated by the frequency divider 124 is decreased as compared with that of FIG. 1.
In the configuration of FIG. 3, the timing for the delivery of the clock signal CLKD from the analog circuit 120 to the digital circuit 110 is critical, which makes the delay adjustment and the like very complicated. In particular, in the audio signal processing circuit, the sampling rate of the audio data varies and the frequencies of the clock signals CLKA and CLKD need to be changed according to the sampling rate. Therefore, the frequency divider 124 is constituted by a variable frequency divider.
Even if the delay adjustment is optimized for a specific sampling rate, timing deviation occurs for another sampling rate. This makes the adoption of the configuration of FIG. 3 more difficult.